System 2018

Introduction

Computer System(I) 2018 Fall

Instructor: 梁阿磊老师

TAs:

Name	Email	QQ
林耘丰	linyunfeng@sjtu.edu.cn	965936317
刘予希	674808516@qq.com	674808516

Course Grading

(Tentative)

• Assignment 1: 10%
• Assignment 2: ~30%
• Final exam: ~60%

Assignments

• Assignment 1 - Adder
  • Adder is an electronic circuit designed to do addition.
  • Task: implement a 16-bit adder in Verilog
• Assignment 2 - RISC-V ISA
  • RISC-V is an open instruction set architecture (ISA) based on established reduced instruction set computing (RISC) principles.
  • Task: implement a CPU in Verilog that implements the RISC-V 32b integer base user-level real-mode ISA (RV32I).

Details see project repository

Policy

(Tentative)

Delayed assignments

Resources

• Textbooks
  • J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 5th Edition: pdf

• Reference Books
  • FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version: pdf
  • 夏宇闻-Verilog经典教程: pdf

• Slides
  • PPT Version：文件:System 2017 Lecture PPT.zip
  • PDF Version：文件:System 2017 Lecture PPT pdf.zip
  • Printed Version： 文件:System 2017 Lecture PPT print.zip

• Course Notes
  • Sidi Lu Version: 文件:System 2017 note Lu.pdf
  • Bingyu Kong Version: 文件:System 2017 note Kong.pdf
  • Peiyao Sheng Version: 文件:System 2017 note Sheng.pdf

• Sites
  • Project repository
  • RISC-V(Green Card)
  • RISC-V ISA Specifications
  • Basys 3 Documentation
  • MIPS ISA implementation by Zhang Zhekai (System 2016)

• Tools
  • FPGA programming
    • Xilinx Vivado 2018.2: jBox link (contact TA if have trouble downloading)
    • iverilog & gtkwave: Windows
  • RISC-V
    • RISC-V GNU Compiler Toolchain:

repo

jBox archive

compiled binaries (obsolete)

config guide by Zhou Fan

Note: run ./configure --prefix=/opt/riscv --with-arch=rv32i --with-abi=ilp32 before making the toolchain. (32-bit soft-float ABI)

• Notes
  • Select xc7a35tcpg236-1 as Xilinx part number when creating Vivado projects.