System(1) 2020

Introduction

Computer System(I) 2019 Fall

Instructor: 梁阿磊老师

TAs:

Name	Email	QQ	WeChat
计家宝	sjcs_jijiabao[at]sjtu.edu.cn	2486948747	question406
柳志轩	lzx993124494[at]sjtu.edu.cn	993124494	L993124494
杨宗翰	fstqwq[at]sjtu.edu.cn	849199382	fstqwq
张宇恒	yveh1999[at]sjtu.edu.cn	1053697976	yveh1999
庄永昊	zhuangyh[at]sjtu.edu.cn	1148830469	ZYH15L

Policy:
- You will have homeworks after class for four times. Please do it on your own.
- The content of your homeworks is about what ALei teaches in class, so listen to the teacher carefully in class.

Overview: RISC-V is an open instruction set architecture (ISA) based on established reduced instruction set computing (RISC) principles.
Task: implement a CPU in Verilog that implements the RISC-V 32b integer base user-level real-mode ISA (RV32I).
For more details, see the link at the bottom of the page

Calendar of the course:

Date	Event
Thu, Sep 17	Release the Verilog exercise
Thu, Sep 24	Release Homework 1
Thu, Oct 8	Deadline of Homework 1
Sun, Oct 11	Release Projects for MS108(toy CPU)
Thu, Oct 15	Release Homework 2
Sun, Oct 25	Release Project for and MS 208(Compiler)
Thu, Oct 29	Deadline of Homework 2
Thu, Nov 5	Release Homework 3
Sun, Nov 8	Deadline of Verilog exercise
Thu, Nov 19	Deadline of Homework 3
Thu, Nov 26	Release Homework 4
Thu, Dec 10	Deadline of Homework 4
Thu, Dec 24	Final Exam
(Maybe) Week 17	Code review for the Project

Calendar of Project:

Weeks	Checkpoint - 5-stage pipelined	Checkpoint - Tomasulo	Checkpoint - OS support	Checkpoint - special
Week 1	Memory controller(read from 2 ports), support arithmetic instruction, no i-cache	Memory controller(read from 2 ports), support arithmetic instruction, no i-cache, no ROB	Same as 5-stage pipelined	Finish all. Believe the potential of human beings
Week 2	Basic design with i-cache	Basic design with i-cache, without ROB	Same as 5-stage pipelined
Week 3	Debug, pass all tests and run on FPGA, now at least 80% of all	Debug, pass all tests and run on FPGA	Same as 5-stage pipelined
Week 4, (ignore dbg from now on)	Add branch prediction, d-cache, now at least 90% of all	Add ROB, add branch prediction	Support CSR instructions and machine mode
Week 5	Try to improve performance	Add ROB, add branch prediction	Support CSR instructions and machine mode
Week 6	End	End	Try to run FreeRTOS with your design.

Textbooks
- J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 5th Edition: pdf

Reference Books
- 自己动手写CPU
- FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version: pdf
- 夏宇闻-Verilog经典教程: pdf

Note: run ./configure --prefix=/opt/riscv --with-arch=rv32i --with-abi=ilp32 before making the toolchain. (32-bit soft-float ABI)

Notes
- Select xc7a35tcpg236-1 as Xilinx part number when creating Vivado projects.