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System(1) 2019

来自ACM Class Wiki

Introduction

Computer System(I) 2019 Fall

Instructor: 梁阿磊老师

TAs:

Name Email QQ
李照宇 apollo19990425@sjtu.edu.cn 2978754465
杨雨欢 yangyuhuan@sjtu.edu.cn 1279551085
李嘉森 lijiasen0921@sjtu.edu.cn 3365815094

Grading

  • Homeworks: 15% (5% + 5% + 5%)
  • Assignment: 35%
  • Final exam: 50%

Homeworks

  • Policy:
    • You will have homeworks after class for three times. Please do it on your own! Believe in yourself!
    • The content of your homeworks is about what Alei teaches in class! Listen to the teacher carefully in class！

Assignment

  • Overview: RISC-V is an open instruction set architecture (ISA) based on established reduced instruction set computing (RISC) principles.
  • Task: implement a CPU in Verilog that implements the RISC-V 32b integer base user-level real-mode ISA (RV32I).
  • Policy:
    • We will give your a lecture about Verilog to help you get start!
    • We will have a midterm-check to check your project and answer your questions. (Maybe after your midterm exam.)
    • Encourage creativity & further exploration (e.g. cache, more effective structure, Tomasulo, etc.) Let your imagination fly!
    • Encourage discussion and question.
    • Discourage copying other's code.

Reference

  • Textbooks
    • J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 5th Edition: pdf
  • Reference Books
    • 自己动手写CPU
    • FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version: pdf
    • 夏宇闻-Verilog经典教程: pdf
  • Tools
    • FPGA programming
      • Xilinx Vivado 2018.2: jBox link (contact TA if have trouble downloading)
      • iverilog & gtkwave: Windows
    • RISC-V
      • RISC-V GNU Compiler Toolchain:
repo
jBox archive
compiled binaries (obsolete)
config guide by Zhou Fan
Note: run ./configure --prefix=/opt/riscv --with-arch=rv32i --with-abi=ilp32 before making the toolchain. (32-bit soft-float ABI)
  • Notes
    • Select xc7a35tcpg236-1 as Xilinx part number when creating Vivado projects.
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