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rCore –
A RISC-V operating system kernel in Rust featuring Sv39 virtual memory, Buddy+Slab allocator,
POSIX-like VFS, and user/kernel isolation.
Mx
Compiler &
JITC –
A full compiler for Mx* (a C-like language) targeting RISC-V via LLVM IR, with OOP support,
and a companion JIT interpreter for LLVM IR.
RISCV-CPU –
A synthesizable out-of-order RISC-V CPU in Verilog using Tomasulo’s algorithm,
deployed on Basys3 FPGA with cache, UART I/O, and exception handling.
Raft Consensus –
Implemented Raft for MIT 6.824, supporting leader election, log replication,
and fault tolerance under network partitions. (Repository not public)
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