start
Differences
This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
start [2012/03/26 07:01] – serailhydra | start [2012/05/19 15:21] (current) – [News] sea | ||
---|---|---|---|
Line 1: | Line 1: | ||
====== News ====== | ====== News ====== | ||
- | **Test Data is updated!** | ||
- | |||
- | The second lecture will be given on **2012.3.26 21:00, SEIEE 3-414**. | ||
- | |||
- | And the deadline of first submission is **2012.3.24 23:59:59**. More detailed solution about delay in submission is under discussion. | ||
- | |||
- | Test Data is generated based on the Green Card. Please follow the Green Card if any confusion about instructions during the implementation. | ||
+ | simics presentation: | ||
======Main Content=== | ======Main Content=== | ||
=====Introduction== | =====Introduction== | ||
Line 24: | Line 18: | ||
* Your 5-stage pipelined CPU should be able to run a required subset of MIPS 32 bit instructions. | * Your 5-stage pipelined CPU should be able to run a required subset of MIPS 32 bit instructions. | ||
* Your design of CPU should contain 2-level caches. | * Your design of CPU should contain 2-level caches. | ||
- | * Your design of CPU should include dynamic branch prediction. | + | * Your design of CPU should include dynamic branch prediction(bonus). |
- Instruction Set | - Instruction Set | ||
* The minimum set of instruction includes: '' | * The minimum set of instruction includes: '' | ||
Line 51: | Line 45: | ||
* Mar 2 6:00pm: Lecture for Pipeline | * Mar 2 6:00pm: Lecture for Pipeline | ||
* Mar 24 23:59:59: Deadline for Pipeline | * Mar 24 23:59:59: Deadline for Pipeline | ||
- | * Mar 28 7:00pm: Lecture for Cache & Advanced Topics | + | * Mar 28 7:30pm: Lecture for Cache & Advanced Topics |
- | * Apr 16(tentative): Optional Module and deadline for Cache Phase | + | * Apr 18 23:59:59: Optional Module |
- | * May 8(tentative): | + | * May 5 1:00pm: Presentation of Advanced Topics |
- | * May 15(tentative): | + | * May 9 23:59:59: Final submission |
+ | * May 12(tentative): | ||
=====Slides=== | =====Slides=== | ||
* Pipeline {{: | * Pipeline {{: | ||
- | * Cache | + | * Cache {{: |
* Optional Module | * Optional Module | ||
- | - Simics | + | - Simics{{: |
- Advanced Mips | - Advanced Mips | ||
=====Submission=== | =====Submission=== | ||
- | * Pipeline {{: | + | * Pipeline {{: |
- | - **Updated data**{{:test-data1.rar|}} | + | - **Results**{{:phase1_result.xlsx|}} |
* Cache | * Cache | ||
+ | - **Results**{{: | ||
* Optional Module | * Optional Module | ||
- Simics | - Simics | ||
Line 86: | Line 82: | ||
* Mips Archive[[http:// | * Mips Archive[[http:// | ||
* Couse page for last year[[http:// | * Couse page for last year[[http:// | ||
+ | * Simics: [[http:// | ||
**Documents** | **Documents** | ||
Line 92: | Line 89: | ||
* Green Card {{: | * Green Card {{: | ||
* slides of liyanmin{{: | * slides of liyanmin{{: | ||
+ | * Simics Installation {{: | ||
+ | * Simics Lab 1 & 2 & 3: {{: | ||
=====Contact=== | =====Contact=== | ||
Diyi Yang(杨笛一) huyaoyang001 [at] gmail.com | Diyi Yang(杨笛一) huyaoyang001 [at] gmail.com |
start.1332745272.txt.gz · Last modified: 2012/03/26 07:01 by serailhydra