News

simics presentation: May 21(Monday)6:00pm-9:20pm at SEIEE 3-414/404/528

Main Content

Introduction

The goal of our project is to design a pipelined, cached processor with some advanced modules.

Verilog is recommended to you as your design language.

Our discussing group is http://groups.google.com/group/mips-acm-sjtu, or you can send email to mips-acm-sjtu@googlegroups.com

Purpose

  • Deepen your understanding of computer hardware concepts such as pipeline, cache and ISA.
  • Learn how to design hardwares using hardware description languages.
  • Learn how to make hardware simulations using standard tools such as ModelSim.

Requirements

  1. Basic Module
    • Your 5-stage pipelined CPU should be able to run a required subset of MIPS 32 bit instructions.
    • Your design of CPU should contain 2-level caches.
    • Your design of CPU should include dynamic branch prediction(bonus).
  2. Instruction Set
    • The minimum set of instruction includes: add, addi, sub, and, andi, beq, bne, j, jal, jr, lw, nor, or, ori, lui, slt, slti, sll, srl, sw
    • You can refer to the “green card” for more details concerning the instructions.
  3. Pipeline Design
    • As this is the core of our project, we will certainly test heavily on correctness and robustness of the pipeline design.
    • You should at least design and implement the pipeline which is described in the textbook.
    • In addition, you can also consult Mr. Li Yamin’s materials if necessary.
    • The difficulty of pipeline design lies in solving several kinds of hazards. This will be discussed later.
  4. Cache and Memory
    • The following requirements should be strictly followed:
      1. The size of data of L1 Cache is fixed to 1KB.
      2. The size of data of L2 Cache is fixed to 16KB.
      3. The size of Memory is fixed to 1MB.
      4. Data and instructions share one memory space. Do not split your memory into two.
    • Notice: only the size of data is limited. Therefore, you are free to design the additional data used in your cache including valid bits, dirty bits and so on. Moreover, you should choose your design of your cache carefully. A bad design of cache will invite great complexity, low efficiency and endless bugs.
  5. Advance Module
    • This is the most exciting part of our project. You can try out whatever you are interested in, but it should be related to CPU design. In past years, we have seen (or witnessed, which is more appropriate):
      1. Linux Schedule Policy
      2. Memory Hierarchy
      3. Instruction Level Parallelism (ILP)
      4. Thread Level Parallelism (TLP)
      5. Cache Coherence
  • Anything relating to CPU design is okay! Try to shock TAs and even yourselves!

Schedule

  • Mar 2 6:00pm: Lecture for Pipeline
  • Mar 24 23:59:59: Deadline for Pipeline
  • Mar 28 7:30pm: Lecture for Cache & Advanced Topics
  • Apr 18 23:59:59: Optional Module First Check and deadline for Cache Phase
  • May 5 1:00pm: Presentation of Advanced Topics
  • May 9 23:59:59: Final submission of Advanced Topics and Simics
  • May 12(tentative): Presentation

Slides

Submission

Tools

Resources

Web Pages

Documents

Contact

Diyi Yang(杨笛一) huyaoyang001 [at] gmail.com

Liuli Chen(陈旒俐)chenliuli.sea [at] gmail.com

Hongyu Zhu(朱虹宇)serailhydra [at] gmail.com

start.txt · Last modified: 2012/05/19 23:21 by sea
 
Recent changes RSS feed Donate Powered by PHP Valid XHTML 1.0 Valid CSS Driven by DokuWiki